EtronTech
EM636327
The DSF signal defines the operation commands
53
DSF
Input
Define Special Function:
in conjunction with the RAS# and CAS# and WE# signals and is latched at
the positive edges of CLK. The DSF input is used to select the masked write
disable/enable command and block write command, and the Special Mode
Register Set cycle.
23, 56, 24, DQM0 - Input
Data Input/Output Mask:
DQM0-DQM3 are byte specific, nonpersistent I/O
57
DQM3
buffer controls. The I/O buffers are placed in a high-z state when DQM is
sampled HIGH. Input data is masked when DQM is sampled HIGH during a
write cycle. Output data is masked (two-clock latency) when DQM is sampled
HIGH during a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-
DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.
97, 98, 100, DQ0- Input/
1, 3, 4, 6 , 7, DQ31 Output
60, 61, 63,
Data I/O:
The DQ0-31 input and output data are synchronized with the
positive edges of CLK. The I/Os are byte-maskable during Reads and Writes.
The DQs also serve as column/byte mask inputs during Block Writes.
64, 68, 69,
71, 72, 9,
10, 12, 13,
17, 18, 20,
21, 74, 75,
77, 78, 80,
81, 83, 84
36-45, 52,
58, 86-95
NC
-
No Connect:
These pins should be left unconnected.
2, 8, 14, 22, VDDQ Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity.
59, 67, 73,
79
5, 11, 19,
62, 70, 76,
82, 99
VSSQ Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
15, 35, 65,
96
VDD Supply
VSS Supply
Power Supply:
Ground
+3.3V±0.3V
16, 46, 66,
85
Preliminary
1998
December
4
ETRON [ ETRON TECHNOLOGY, INC. ]
