EtronTech
EM636165
Ball Assignment (Top View)
Pin Assignment (Top View)
1
2
3
4
5
6
7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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26
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE#
CAS#
RAS#
CS#
A11
A10
A0
1
2
3
4
5
6
7
8
Vss
DQ0
A
B
C
D
E
F
VDD
VSS
DQ15
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
DQ1
DQ2
DQ3
DQ14
VDDQ
VSSQ
DQ4
VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDQ DQ5
VSSQ DQ6
DQ9
DQ8
VDDQ
NC
DQ7
NC
G
H
NC
NC
NC
NC
NC
NC
LDQM
J
K
L
WE#
UDQM
RAS#
NC
NC
A0
CLK
CAS#
CS#
NC
A7
A6
A5
A4
A1
A2
A3
VDD
NC
A9
CKE
A11
A8
M
N
Vss
A10
A7
A5
A4
A2
A1
P
R
A6
A3
VDD
VSS
Overview
The EM636165 SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured
as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command
which is then followed by a Read or Write command.
The EM636165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst
termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a
programmable mode register, the system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth and particularly well suited to high
performance PC applications
Preliminary
2
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
