EtronTech
EM636165
1M x 16 SDRAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
BANKA
ACTIVATE
COMMAND
NOP
NOP
NOP
READ A
WRITE A
NOP
DIN A
DIN A
NOP
NOP
DIN
CAS# latency=1
DIN
DIN
A
A
DIN
DIN
A
A
A
A
0
0
1
1
2
2
3
3
t
, DQ's
CK1
Must be Hi-Z before
the Write Command
CAS# latency=2
DIN
t
, DQ's
CK2
: "H" or "L"
Read to Write Interval
(Burst Length 4, CAS# Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
NOP
NOP
WRITE B
DIN B
NOP
NOP
NOP
NOP
READ A
CAS# latency=1
DOUT A
DIN B
DIN B
DIN B
0
0
0
1
2
3
t
, DQ's
CK1
Must be Hi-Z before
the Write Command
CAS# latency=2
, DQ's
DIN B
DIN B
1
DIN B
DIN B
t
2
3
CK2
: "H" or "L"
Read to Write Interval
(Burst Length 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Bank,
Row
ADDRESS
Bank(s)
Col
A
tRP
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
Precharge
DOUT A
NOP
Activate
CAS# latency=1
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
, DQ's
CK1
CAS# latency=2
, DQ's
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK2
CAS# latency=3
, DQ's
DOUT A
DOUT A
2
DOUT A
DOUT A
0
1
3
t
CK3
Read to Precharge
(CAS# Latency = 1, 2, 3)
Preliminary
9
Rev. 2.7 Mar. 2006
ETRON [ ETRON TECHNOLOGY, INC. ]
