Et r on Tech
EM566169BC
AC Test Condition
Output load : 30pF + one TTL gate
Input pulse level : 0.4V, 2.4
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Timing measurements : 0.5 x V
CC
tR, tF : 5ns
AC Test Loads
RL = 50 Ω
VL = 1.5 V
DOUT
CL1 = 30 pF
Z0 = 50 Ω
Note:
1. Including scope and jig capacitance
State Diagram
Deep Power Down Exit Sequence
CE1# = VIH or VIL,
CE2=VIH
Deep Power
Down Mode
CE2=VIH
CE2=VIL
Initial State
(Wait 200µs)
Power
on
Active
CE1# =VIL,
CE2=VIH,
CE2=VIL
CE2=VIH,
CE1# =VIH
Power Up Sequence
or UB#, LB#
=VIH
Standby
Standby Mode Characteristics
Power Mode
Standby
Memory Cell Data
Standby Current (µA)
Wait Time
0 ns
Valid
100
10
Deep Power Down
Invalid
200 µs
7
Rev 0.6
Apr. 2004
ETRON [ ETRON TECHNOLOGY, INC. ]
