ES4318 PRODUCT BRIEF
Name
TDMDX
RSEL
Number
I/O
O
I
Definition
TDM transmit data.
ROM Select
RSEL
Selection
16-bit ROM
8-bit ROM
25
0
1
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
28
29
30
31
I
I
TDM receive data.
TDM clock input.
TDM frame synch.
I
O
O
I
TDM output enable, active low.
Audio transmit frame sync.
Select PLL1.
32
SEL_PLL1
TSD
O
I
Audio transmit serial data port.
Select PLL0.
SEL_PLL0
SEL_PLL2
SEL_PLL0
Clock Output
2.5 x DCLK
3 x DCLK
0
0
1
1
0
1
0
1
33
3.5 x DCLK
4 x DCLK
SEL_PLL2
MCLK
36
Select PLL2. See the table for pin number 33.
Audio master clock for audio DAC.
Audio transmit bit clock.
S/PDIF (IEC958) Format Output.
Audio receive serial data.
Audio receive frame synch.
Audio receive bit clock.
39
I/O
I/O
O
I
TBCK
40
SPDIF_DOBM
RSD
41
45
RWS
46
I
RBCK
47
I
APLLCAP
XIN
48
I
Analog PLL Capacitor.
49
50
I
Crystal input.
XOUT
O
O
O
O
I
Crystal output.
DMA[11:0]
DCAS#
66:61,58:53
69
DRAM address bus.
Column address strobe, active low.
Output enable, active low.
Clock Enable, active low.
DRAM write enable, active low.
Row address strobe, active low.
DRAM data bus.
DOE#
70
DSCK_EN
DWE#
71
O
O
I/O
O
O
O
I
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
DQM
74:72
96:93,90:85,82:77
97,100
SDRAM chip select [1:0], active low.
Data input/output mask.
Clock to SDRAM.
101
DSCK
102
DCLK
105
Clock Input (27 MHz)
YUV[7:0]
PCLK2XSCN
PCLKQSCN
VSYNCH#
HSYNCH#
115:113,110:106
O
I/O
I/O
I/O
I/O
O
O
O
I
8-bit YUV output.
116
117
118
119
2X pixel clock.
Pixel clock.
Vertical sync for screen video interface, programmable for rising or falling edge, active low.
Horizontal sync for screen video interface, programmable for rising or falling edge, active low.
Host data bus
HD[15:0]
HCS1FX#
HCS3FX#
HIOCS16#
HA[2:0]
141:140,137:131,128:122
152
Host select 1.
153
Host select 3.
151
Device 16-bit data transfer.
Host address bus.
158, 155:154
I/O
I
VPP
159
Peripheral protection voltage.
Host write/DCI Interface Acknowledge Signal, active low.
Host read/DCI Interface Clock.
Host data bus.
HWR#/DCI_ACK#
HRD#/DCI_CLK
HD[15:0]
HWRQ#
HRDQ#
149
I,I
I,I
I/O
O
O
I/O
O
I
150
141:140,137:131,128:122
142
Host write request.
143
Host read request.
HIRQ
144
Host interrupt.
HRST#
145
Host reset.
HIORDY
HWR#
146
Host I/O ready.
149
O
I/O
O
O
I/O
O
O
Host write request.
AUX[7:0]
LOE#
169:165,162:160
Auxiliary ports.
170
Device output enable, active low.
Chip select [3:0], active low.
Device data bus.
LCS[3:0]#
LD[15:0]
LWRLL#
LWRHL#
NC
176:173
197:194, 191:185, 182:178
198
Device write enable, active low.
Device write enable, active low.
No connect.
199
37,38,42,203:202
ESS Technology, Inc.
SAM0377-052101
3
ESS [ ESS Technology,Inc ]
