ESMT
M24L816512SA
AC Test Loads and Waveforms
Parameters
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
R1
R2
RTH
VTH
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]
-55
-70
Parameter
Read Cycle
Description
Unit
Min.
55[14]
5
Max.
Min.
70
Max.
tRC
Read Cycle Time
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
Data Hold from Address Change
5
55
25
70
35
CE LOW to Data Valid
tDOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
5
5
5
5
OE LOW to LOW Z[11, 12]
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11, 12]
CE HIGH to High Z[11, 12]
BLE /BHE LOW to Data Valid
BLE /BHE LOW to Low Z[11, 12]
25
25
25
55
25
70
tLZBE
tHZBE
tSK[14]
5
5
10
0
25
10
BLE /BHE HIGH to High Z[11, 12]
Address Skew
Notes:
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V CC(typ)/2, input pulse levels of 0V
to V CC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance
11. tHZOE, tHZCE, tHZBE, and tHZWEtransitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.5 5/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
