ESMT
M24L416256SA
AC Test Loads and Waveforms
Parameters
3.0V VCC
22000
22000
11000
1.50
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
V
Switching Characteristics (Over the Operating Range)[10]
–55
–60
–70
Prameter
Description
Unit
Min.
55
Max.
Min.
60
Max.
Min.
70
Max.
Read Cycle
tRC
tAA
tOHA
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
ns
ns
ns
55
60
70
5
8
10
tACE
55
25
60
25
70
35
ns
ns
ns
ns
ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[11, 13]
OE HIGH to High Z[11, 13]
CE LOW to Low Z[11, 13]
tDOE
tLZOE
tHZOE
tLZCE
5
2
5
2
5
5
25
25
25
tHZCE
tDBE
25
55
25
60
25
70
ns
ns
ns
CE HIGH to High Z[11, 13]
BLE / BHE LOW to Data Valid
tLZBE
5
5
5
BLE /BHE LOW to Low Z[11, 13]
tHZBE
10
0
10
5
25
10
ns
ns
BLE /BHE HIGH to High-Z[11, 13]
Address Skew
[14]
tSK
Write Cycle[12]
tWC
Write Cycle Time
55
45
60
45
70
60
ns
ns
tSCE
CE LOW to Write End
tAW
tHA
tSA
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
45
0
0
45
0
0
55
0
0
ns
ns
ns
tPWE
40
40
45
ns
WE Pulse Width
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ)/2, input pulse levels of 0V to V CC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test
Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4 5/14
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
