ESMT
M13S64164A (2Y)
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
-4
-5
-6
Symbol
Unit
Note
Parameter
min
7.5
6
max
12
min
7.5
6
max
12
min
7.5
6
max
12
CL2
CL2.5
CL3
ns
Clock period
tCK
12
12
12
4
12
5
12
6
12
DQ output access time from
CLK/ CLK
tAC
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
CLK high-level width
CLK low-level width
tCH
tCL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
DQS output access time from
CLK/ CLK
tDQSCK
-0.6
+0.6
1.25
-0.6
+0.6
1.25
-0.6
+0.6
1.25
ns
Clock to first rising edge of DQS delay
DQ and DM input setup time (to DQS)
DQ and DM input hold time (to DQS)
tDQSS
tDS
0.72
0.4
0.72
0.4
0.75
0.45
0.45
tCK
ns
ns
tDH
0.4
0.4
DQ and DM input pulse width
(for each input)
tDIPW
tIS
1.75
0.6
0.6
0.7
0.7
2.2
1.75
0.6
0.6
0.7
0.7
2.2
1.75
0.75
0.75
0.8
ns
ns
ns
ns
ns
ns
18
Address and Control input setup time
(fast)
15,17~19
15,17~19
16~19
16~19
18
Address and Control input hold time
(fast)
tIH
Address and Control input setup time
(slow)
tIS
Address and Control input hold time
(slow)
tIH
0.8
Control and Address input pulse width
(for each input)
tIPW
2.2
DQS input high pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.35
0.35
0.2
0.35
0.35
0.2
tCK
tCK
tCK
tCK
ns
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Data strobe edge to output data edge
tDSH
0.2
0.2
0.2
tDQSQ
0.4
0.4
0.4
22
11
Data-out high-impedance time from
CLK/ CLK
tHZ
tLZ
tHP
+0.7
+0.7
+0.7
ns
ns
ns
Data-out low-impedance time from
CLK/ CLK
-0.7
+0.7
0.5
-0.7
+0.7
0.5
-0.7
+0.7
0.5
11
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
Clock half period
20,21
21
DQ/DQS output hold time from DQS
Data hold skew factor
tQH
t
HP- tQHS
t
HP- tQHS
tHP- tQHS
ns
ns
tQHS
Elite Semiconductor Memory Technology Inc.
Publication Date : Apr. 2012
Revision : 1.0 9/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
