ESMT
DDR SDRAM
Features
M13S2561616A
Operation Temperature Condition -40~85°C
4M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z
z
z
z
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
z
z
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
z
z
z
z
z
z
z
z
z
z
z
z
z
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V
Auto & Self refresh
7.8us refresh interval
SSTL-2 I/O interface
66pin TSOPII and 60 ball BGA package
Ordering information :
PRODUCT NO.
MAX FREQ
200MHz
166MHz
200MHz
166MHz
VDD
PACKAGE
COMMENTS
M13S2561616A -5TIG
M13S2561616A -6TIG
M13S2561616A -5BIG
M13S2561616A -6BIG
2.5V
TSOPII
Pb-free
2.5V
BGA
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1 2/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
