ESMT
M13S2561616A (2A)
IDD Parameters and Test Conditions
Test Condition
Symbol
Note
Operating Current (one bank Active - Precharge):
t
RC = tRC (min); tCK = tCK (min); DQ, DM, and DQS inputs changing once per clock cycle;
IDD0
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; tRC = tRC (min); tCK = tCK (min); IOUT = 0mA;
IDD1
IDD2P
IDD2F
2
Address and control inputs changing once per deselect cycle; CS = high between valid commands
Precharge Power-down Standby Current:
All banks idle; Power-down mode; tCK = tCK (min); CKE ≤ VIL(max); VIN = VREF for DQ, DQS and DM.
Precharge Floating Standby Current:
CS ≥ VIH(min); All banks idle; CKE ≥ VIH(min); tCK = tCK (min);
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM.
Precharge Quiet Standby Current:
IDD2Q
IDD3P
CS ≥ VIH(min); All banks idle; CKE ≥ VIH(min); tCK = tCK (min);
Address and other control inputs stable at ≥ VIH(min) or ≤ VIL(max); VIN = VREF for DQ, DQS, and DM.
Active Power-down Standby Current:
One bank active; Power-down mode; CKE ≤ VIL(max); tCK = tCK (min); VIN = VREF for DQ, DQS, and DM.
Active Standby Current:
CS ≥ VIH(min); CKE ≥ VIH(min); One bank active; tRC = tRAS (max); tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
IDD3N
IDD4R
IDD4W
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min); IOUT = 0mA;
50% of data changing on every transfer.
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
Auto Refresh Current:
IDD5
IDD6
t
RC = tRFC(min)
Self Refresh Current:
1
2
CKE ≤ 0.2V; external clock on; tCK = tCK (min)
Operating Current (Four bank operation):
IDD7
Four-bank interleaving READs (burst = 4) with auto precharge; tRC = tRC (min); tCK = tCK (min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; IOUT = 0mA.
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.4 6/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
