ESMT
M13S2561616A (2K)
Operation Temperature Condition -40°C~85°C
PIN CONFIGURATION (TOP VIEW)
(TSOPII 66L, 400milX875mil Body, 0.65mm Pin Pitch )
BALL CONFIGURATION (TOP VIEW)
(BGA60, 8mmX13mmX1.2mm Body, 0.8mm Ball Pitch)
1
2
3
7
8
9
VDD
DQ0
VDDQ
VSSQ
DQ15
VSS
A
B
C
D
E
F
VSSQ
DQ14 VDDQ DQ13
DQ12 VSSQ DQ11
DQ2
DQ4
DQ6
DQ1
DQ3
VDDQ
VSSQ
DQ10 VDDQ
DQ9
DQ5
DQ7
LDQS VDDQ
DQ8
VSSQ
VSS
UDQS
VREF
LDM
WE
VDD
CAS
NC
UDM
CLK
G
H
J
CLK
CS
BA0
A10/AP
A1
A12
A11
A8
CKE
A9
RAS
BA1
K
L
A0
A2
A7
A6
A5
M
A4
VDD
A3
VSS
Pin Description
Pin Name
Function
Pin Name
Function
Address inputs
- Row address A0~A12
DM is an input mask signal for write data.
LDM corresponds to the data on DQ0~DQ7;
UDM correspond to the data on DQ8~DQ15.
A0~A12,
- Column address A0~A8
A10/AP: AUTO Precharge
BA0, BA1: Bank selects (4 Banks)
LDM, UDM
BA0, BA1
DQ0~DQ15 Data-in/Data-out
Clock input
CLK, CLK
CKE
Row address strobe
Column address strobe
Write enable
Clock enable
RAS
CAS
Chip select
CS
VDDQ
VSSQ
VREF
Supply Voltage for DQ
Ground for DQ
WE
VSS
Ground
VDD
Power
Reference Voltage for SSTL_2
Bi-directional Data Strobe.
LDQS, UDQS
NC
No connection
LDQS corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on DQ8~DQ15.
Elite Semiconductor Memory Technology Inc.
Publication Date : May 2010
Revision : 1.2
3/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
