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M13S2561616A-6TIG2K 参数 Datasheet PDF下载

M13S2561616A-6TIG2K图片预览
型号: M13S2561616A-6TIG2K
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 49 页 / 1234 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S2561616A (2K)  
Operation Temperature Condition -40°C~85°C  
AC Timing Parameter & Specifications (Note: 1~6, 9~10)  
-5  
-6  
Symbol  
Unit  
Note  
Parameter  
min  
7.5  
5
max  
12  
min  
7.5  
6
max  
12  
CL2  
CL2.5  
CL3  
ns  
ns  
Clock period  
tCK  
12  
12  
5
12  
6
12  
tAC  
-0.7  
+0.7  
-0.7  
+0.7  
DQ output access time from CLK/ CLK  
CLK high-level width  
tCH  
tCL  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tCK  
tCK  
CLK low-level width  
tDQSCK  
-0.55  
+0.55  
1.25  
-0.6  
+0.6  
1.25  
ns  
DQS output access time from CLK/ CLK  
Clock to first rising edge of DQS delay  
DQ and DM input setup time (to DQS)  
DQ and DM input hold time (to DQS)  
tDQSS  
tDS  
tDH  
tDIPW  
tIS  
0.72  
0.45  
0.45  
1.75  
0.7  
0.72  
0.45  
0.45  
1.75  
0.7  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DQ and DM input pulse width (for each input)  
Address and Control input setup time (fast)  
Address and Control input hold time (fast)  
Address and Control input setup time (slow)  
Address and Control input hold time (slow)  
18  
15,17~19  
15,17~19  
16~19  
tIH  
0.7  
0.7  
tIS  
0.9  
0.9  
tIH  
0.9  
0.9  
16~19  
Control and Address input pulse width (for  
each input)  
tIPW  
2.2  
2.2  
ns  
18  
DQS input high pulse width  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
0.35  
0.35  
0.2  
tCK  
tCK  
tCK  
tCK  
ns  
DQS input low pulse width  
DQS falling edge to CLK setup time  
DQS falling edge hold time from CLK  
Data strobe edge to output data edge  
tDSH  
0.2  
0.2  
tDQSQ  
0.4  
0.4  
22  
11  
tHZ  
tLZ  
tHP  
+0.7  
+0.7  
ns  
ns  
ns  
Data-out high-impedance time from CLK/ CLK  
Data-out low-impedance time from CLK/ CLK  
Clock half period  
-0.7  
+0.7  
-0.7  
+0.7  
11  
tCLmin or  
tCHmin  
tCLmin or  
tCHmin  
20,21  
21  
DQ/DQS output hold time from DQS  
Data hold skew factor  
tQH  
tQHS  
tRAS  
tRC  
t
HP- tQHS  
t
HP- tQHS  
ns  
ns  
ns  
ns  
0.5  
0.5  
Active to Precharge command  
40  
55  
70K  
42  
60  
70K  
Active to Active /Auto Refresh command period  
Auto Refresh to Active / Auto Refresh  
command period  
tRFC  
70  
72  
ns  
Active to Read, Write delay  
tRCD  
tRP  
tRAP  
tRRD  
15  
15  
15  
10  
18  
18  
18  
12  
ns  
ns  
ns  
ns  
Precharge command period  
Active to Read with Auto Precharge command  
Active bank A to Active bank B command  
Elite Semiconductor Memory Technology Inc.  
Publication Date : May 2010  
Revision : 1.2 9/49