ESMT
M13S128168A
AC Timing Parameter & Specifications-continued
-4
-5
-6
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
tCLmin or
tCLmin or
tCLmin or
Half Clock Period
tHP
-
-
-
ns
t
CHmin
tHP-tQHS
-
t
CHmin
tHP-tQHS
-
t
CHmin
tHP-tQHS
-
DQ-DQS output hold time
Data hold skew factor
tQH
tQHS
tRAS
tRC
-
-
-
ns
ns
ns
ns
ns
ns
ns
0.5
0.45
0.5
ACTIVE to PRECHARGE command
Row Cycle Time
40
70K
40
70K
42
70K
52
-
-
-
-
60
-
-
-
-
60
-
-
-
-
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
tRFC
tRCD
tRP
60
70
72
15
15
18
15
15
18
ACTIVE to READ with
AUTOPRECHARGE command
tRAP
tRRD
18
10
-
-
18
10
-
-
18
12
-
-
ns
ns
ACTIVE bank A to ACTIVE bank B
command
Write recovery time
tWR
tWTR
15
2
-
-
15
2
-
-
15
2
-
-
ns
tCK
tCK
us
Write data in to READ command delay
Col. Address to Col. Address delay
Average periodic refresh interval
Write preamble
tCCD
1
-
1
-
1
-
tREFI
tWPRE
tWPST
tRPRE
tRPST
-
15.6
-
-
15.6
-
-
15.6
-
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
0.25
0.4
0.9
0.4
tCK
tCK
tCK
tCK
Write postamble
0.6
1.1
0.6
0.6
1.1
0.6
0.6
1.1
0.6
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup
time
tWPRES
0
-
0
-
0
-
ns
Load Mode Register / Extended Mode
register cycle time
tMRD
tXSRD
tXSNR
2
-
-
-
2
-
-
-
1
-
-
-
tCK
tCK
ns
Exit self refresh to READ command
200
75
200
75
200
75
Exit self refresh to non-READ
command
(tWR/tCK
)
(tWR/tCK
)
(tWR/tCK
)
Autoprecharge write
recovery+Precharge time
+
+
+
tDAL
-
tCK
(tRP/tCK
)
(tRP/tCK
)
(tRP/tCK)
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 2.2 7/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
