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M13S128324A-6LIG 参数 Datasheet PDF下载

M13S128324A-6LIG图片预览
型号: M13S128324A-6LIG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行双倍数据速率SDRAM [1M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 49 页 / 882 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M13S128324A  
Operation Temperature Condition -40~85°C  
AC Timing Parameter & Specifications-continued  
-5  
-6  
Symbol  
Unit  
Parameter  
Min  
Max  
Min  
Max  
tCLmin  
or  
tCLmin  
or  
tCHmin  
-
-
Half Clock Period  
tHP  
tQH  
tRAS  
tRC  
ns  
ns  
t
CHmin  
tHP-0.  
45  
tHP-0.  
5
DQ-DQS output hold time  
-
-
ACTIVE to PRECHARGE  
command  
120K  
ns  
120K  
ns  
8
7
tCK  
tCK  
tCK  
Row Cycle Time  
12  
14  
-
-
10  
12  
-
-
AUTO REFRESH Row Cycle  
Time  
tRFC  
ACTIVE to READ,WRITE  
delay  
tRCD  
tRP  
4
4
-
-
3
3
-
-
tCK  
tCK  
PRECHARGE command  
period  
ACTIVE to READ with  
AUTOPRECHARGE  
command  
tRAP  
4
-
3
-
tCK  
ACTIVE bank A to ACTIVE  
bank B command  
tRRD  
tWR  
2
15  
2
-
-
-
2
15  
2
-
-
-
tCK  
ns  
tCK  
Write recovery time  
Write data in to READ  
command delay  
tWTR  
Col. Address to Col. Address  
delay  
tCCD  
tREFI  
1
-
-
1
-
-
tCK  
us  
Average periodic refresh  
interval  
7.8  
7.8  
Write preamble  
tWPRE  
tWPST  
tRPRE  
tRPST  
0.25  
0.4  
-
0.25  
0.4  
-
tCK  
tCK  
tCK  
tCK  
Write postamble  
0.6  
1.1  
0.6  
0.6  
1.1  
0.6  
DQS read preamble  
DQS read postamble  
0.9  
0.9  
0.4  
0.4  
Clock to DQS write preamble  
setup time  
tWPRES  
0
2
-
-
0
2
-
-
ns  
Load Mode Register /  
Extended Mode register  
cycle time  
tMRD  
tCK  
Exit self refresh to READ  
command  
tXSRD  
tXSNR  
200  
75  
-
-
200  
-
-
tCK  
ns  
Exit self refresh to  
non-READ command  
75  
(tWR/tC  
K) +  
(tRP/tC  
(tWR/tC  
Autoprecharge write  
recovery+Precharge time  
)
K
tDAL  
-
-
tCK  
+(tRP/t  
)
)
K
CK  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Dec. 2007  
Revision : 1.0  
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