ESMT
M12S16161A
Operation Temperature Condition -40°C~85°C
Mode Register
BA A10 A9
A8
0
A8
0
A7
1
A7
0
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
0
0
0
JEDEC Standard Test Set (refresh counter test)
BA A10 A9
x
x
1
LTMODE
WT
BL
Burst Read and Single Write (for Write
Through Cache)
BA A10 A9
A8
1
A7
0
A6 A5 A4 A3 A2 A1 A0
Use in future
BA A10 A9
A8
1
A7
1
A6 A5 A4 A3 A2 A1 A0
x
x
x
v
v
v
v
v
v
v
Vender Specific
v =Valid
BA A10 A9
A8
0
A7
0
A6 A5 A4 A3 A2 A1 A0
0
0
0
LTMODE
WT
BL
Mode Register Set
x =Don’t care
Bit2-0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
WT=1
1
2
4
8
R
R
R
R
Burst length
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
CAS Latency
000
001
010
011
100
101
110
111
R
R
2
Latency mode
3
R
R
R
R
Mode Register Write Timing
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A10, BA
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2007
Revision : 1.0 7/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
