ESMT
M12L64164A
Operation Temperature Condition -40°C~85°C
SDRAM
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
PRODUCT NO. MAX FREQ. PACKAGE Comments
y
y
y
y
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
M12L64164A-5TIG
M12L64164A-6TIG
200MHz
166MHz
54 TSOP II
54 TSOP II
Pb-free
Pb-free
M12L64164A-7TIG
M12L64164A-5BIG
M12L64164A-6BIG
M12L64164A-7BIG
143MHz
200MHz
166MHz
143MHz
54 TSOP II
54 VBGA
54 VBGA
54 VBGA
Pb-free
Pb-free
Pb-free
Pb-free
y
y
y
y
DQM for masking
Auto & self refresh
15.6 μ s refresh interval
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
54 Ball FVBGA (8mmx8mm)
1
2
3
4
5
6
7
8
9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
1
VDD
DQ0
VDDQ
DQ1
DQ2
VS SQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VS SQ
DQ7
VDD
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
2
VDDQ
DQ15
VSSQ
DQ0
VDD
A
B
VSS
3
4
5
VSSQ
VDDQ
DQ2
DQ4
DQ1
DQ3
DQ14
DQ12
DQ13
DQ11
VDDQ
VSSQ
6
7
C
D
E
F
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VSSQ
VDD
VDDQ
VSS
DQ6
DQ10
DQ8
DQ9
NC
DQ5
DQ7
LDQM
NC
LDQM
WE
UDQM
NC
CLK
A11
CKE
A9
CAS
A13
RAS
A12
WE
CS
UDQM
CLK
CKE
NC
CAS
RAS
CS
G
H
J
A11
A13
A8
A10
A7
A5
A6
A4
A0
A3
A1
A2
A9
A12
A8
A10/AP
A0
VSS
VDD
A7
A6
A1
A5
A2
A4
A3
VSS
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2007
Revision: 1.2 2/45