ESMT
M12L64164A
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
PARAMETER
Input levels (Vih/Vil)
VALUE
2.4/0.4
1.4
UNIT
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
Vtt = 1.4V
3.3V
50
1200
Ω
Ω
VOH (DC) =2.4V , IOH = -2 mA
VOL (DC) =0.4V , IOL = 2 mA
Output
Output
Z0 =50Ω
50pF
50pF
870
Ω
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
SYMBOL
UNIT
NOTE
-5
10
15
-6
12
18
-7
14
20
Row active to row active delay
tRRD(min)
ns
ns
1
1
t
RCD(min)
RAS to CAS delay
Row precharge time
tRP(min)
15
38
18
40
100
58
60
1
20
42
ns
ns
1
1
tRAS(min)
Row active time
t
RAS(max)
RC(min)
RFC(min)
us
t
@ Operating
Row cycle time
@ Auto refresh
53
55
63
70
ns
1
1,5
2
t
ns
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CLK
CLK
2
2
1
1
CLK
CLK
2
3
Col. address to col. address delay
CAS latency = 3
CAS latency = 2
2
1
Number of valid
Output data
ea
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 3.4 5/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
