ESMT
M12L64322A (2U)
BLOCK DIAGRAM
CLK
Clock
Generator
Bank D
Bank C
Bank B
CKE
Row
Address
Buffer
&
Refresh
Counter
Address
Bank A
Mode
Register
Sense Amplifier
Column Decoder
DQM0~3
Column
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Data Control Circuit
DQ
PIN DESCRIPTION
PIN
NAME
System Clock
INPUT FUNCTION
CLK
CS
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQM0-3.
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
A0 ~ A10
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0 , BA1
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
RAS
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
Column Address Strobe
CAS
CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM0~3
Data Input / Output Mask
DQ0 ~ DQ31
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
VDD / VSS
Power Supply / Ground
Data Output Power /
Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ
NC
No Connection
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
3/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
