ESMT
M12L128168A
Operation temperature condition -40°C ~85°C
Version
Parameter
Col. address to col. address delay
Symbol
Unit
tCK
Note
-5
-6
1
-7
tCCD(min)
3
4
CAS latency = 3
CAS latency = 2
2
Number of valid
Output data
ea
1
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μ s.)
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-5
-6
-7
Parameter
Symbol
Unit
Note
MIN
MAX MIN
MAX MIN
MAX
CAS latency = 3
5
6
1000
7
1000
CLK cycle time
tCC
ns
1
1000
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
10
10
10
4.5
6
5.4
6
5.4
6
CLK to valid
output delay
tSAC
ns
ns
1,2
2
2
2
2.5
2.5
2.5
2.5
1.5
1
2.5
2.5
2.5
2.5
1.5
1
Output data
hold time
tOH
CLK high pulsh width
CLK low pulsh width
Input setup time
tCH
tCL
2
ns
ns
ns
ns
ns
3
3
3
3
2
2
tSS
tSH
tSLZ
1.5
1
Input hold time
CLK to output in Low-Z
1
1
1
CAS latency = 3
CAS latency = 2
4.5
5.4
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
-
6
6
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2007
Revision: 1.2 6/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
