ESMT
M12L128168A (2L)
BLOCK DIAGRAM
CLK
Clock
Generator
Bank D
Bank C
Bank B
CKE
Row
Address
Address
Buffer
&
Refresh
Counter
Bank A
Mode
Register
Sense Amplifier
Column Decoder
L(U)DQM
Column
Address
Buffer
&
CS
RAS
CAS
WE
Data Control Circuit
Counter
DQ
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Chip Select
CS
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
A0 ~ A11
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0 , BA1
RAS
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Column Address Strobe
Write Enable
CAS
WE
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ DQ15
VDD / VSS
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power Supply / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ
NC
Data Output Power / Ground
No Connection
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.3
2/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
