ESMT
(Preliminary)
F25S04PA
Table 3: F25S04PA Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
TB
X
0
BP2
0
BP1
0
BP0
0
Block Range
None
Address Range
0
None
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/8
Lower 1/4
Lower 1/2
All Blocks
0
0
1
Block 7
070000H – 07FFFFH
060000H – 07FFFFH
040000H – 07FFFFH
000000H – 00FFFFH
000000H – 01FFFFH
000000H – 03FFFFH
000000H – 07FFFFH
0
0
1
0
Block 6~7
Block 4~7
Block 0
0
0
1
1
1
0
0
1
1
0
1
0
Block 0~1
Block 0~3
Block 0~7
1
0
1
1
X
1
X
X
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2
7/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
