ESMT
F25S004A
Instructions
Instructions are used to Read, Write (Erase and Program), and
configure the device. The instruction bus cycles are 8 bits each
for commands (Op Code), data, and addresses. Prior to
executing any Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, or Chip-Erase
instructions, the Write-Enable (WREN) instruction must be
executed first. The complete list of the instructions is provided in
Table 5. All instructions are synchronized off a high to low
SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first
transition of CE . Inputs will be accepted on the rising edge of
TABLE 5: DEVICE OPERATION INSTRUCTIONS
Bus Cycle
Cycle Type/
Operation1,2
Max
Freq
1
2
3
4
5
6
SIN
SOUT
SIN
SOUT SIN
SOUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SIN SOUT SIN SOUT SIN SOUT
Read
33 MHz 03H
0BH
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z A23-A16 Hi-Z A15-A8
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0 Hi-Z
A7-A0 Hi-Z
X
X
-
DOUT
X
-
High-Speed-Read
X
-
-
DOUT
-
-
Sector-Erase4,5 (4K Byte)
20H
D8H
Block-Erase5 (64K Byte)
-
-
60H
C7H
02H
Chip-Erase5
Byte-Program5
Auto-Address-Increment-word
programming (AAI)6
Read-Status-Register
(RDSR)
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
Hi-Z A23-A16 Hi-Z A15-A8
Hi-Z
Hi-Z
A7-A0 Hi-Z DIN Hi-Z
ADH Hi-Z A23-A16 Hi-Z A15-A8
A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z
05H
50H
01H
Hi-Z
Hi-Z
X
-
DOUT
-
-
-
-
Note7
-
-
Note7
-
-
-
Note7
-
-
-
-
-
-
Enable-Write-Status-Register
-
-
-
-
-
-
(EWSR)8
Write-Status-Register
(WRSR)8
Write-Enable (WREN) 11
Hi-Z Data Hi-Z
-.
50MHz
06H
04H
ABH
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write-Disable (WRDI)
Read-Electronic-Signature9
(RES)
X
12H
Jedec-Read-ID (JEDEC-ID) 10
Read-ID (RDID)
9FH
Hi-Z
X
8CH
X
20H
Hi-Z
X
13H
-
-
-
-
90H (A0=0)
8CH
12H
12H
8CH
Hi-Z A23-A16 Hi-Z A15-A8
A7-A0 Hi-Z
X
X
90H (A0=1)
Enable SO to output RY/BY#
Status during AAI (EBSY)
Disable SO to output RY/BY#
Status during AAI (DBSY)
70H
80H
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1. Operation: SIN = Serial In, SOUT = Serial Out
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
3. One bus cycle is eight clock periods.
4. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
5. Prior to any Byte-Program, Sector-Erase, Block-Erase,or Chip-Erase operation, the Write-Enable (WREN) instruction must be
executed.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by the data to be
programmed.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction
of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
9. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.1 9/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
