ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Bus Cycle 1~3
4
SOUT SIN SOUT SIN SOUT SIN
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Max.
Freq
Operation
1
2
3
5
6
N
SIN
SOUT
SIN
SOUT
SIN
X
X
SOUT
SIN SOUT
Read
33 MHz 03H
X
X
DOUT0
X
DOUT1
DOUT0
X
X
cont.
cont.
Fast Read
0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
3BH A23-A16 A15-A8 A7-A0
Fast Read Dual
X
DOUT0~1
cont.
Output12,13
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
60H /
-
-
-
-
-
-
-
-
-
-
-
-
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
Up to
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
ADH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
Hi-Z
DIN1
Hi-Z
256 Hi-Z
bytes
Auto Address Increment
word programming5 (AAI)
Read Status Register
(RDSR) 6
Hi-Z
DIN1
Hi-Z
-
-
-
-
-
-
05H Hi-Z
50H Hi-Z
X
-
DOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Enable Write Status
Register (EWSR) 7
Write Status Register
(WRSR) 7
50MHz
01H Hi-Z
06H Hi-Z
04H Hi-Z
DIN
Hi-Z
-
-
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Enable (WREN) 10
Write Disable (WRDI)/
Exit secured OTP mode
Enter secured OTP mode
(ENSO)
-
-
-
-
-
B1H Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
9FH Hi-Z
90H Hi-Z
-
X
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100MHz
Read Electronic
13H
33H
73H
8CH
-
-
Signature (RES) 8
RES in secured OTP
mode & not lock down
RES in secured OTP
mode & lock down
Jedec Read ID
X
-
-
-
-.
-.
X
-
-
X
-
X
X
20H
14H
(JEDEC-ID) 9
00H Hi-Z
01H Hi-Z
X
X
8CH
13H
X
X
13H
8CH
-
-
-
-
Read ID (RDID) 11
00H
Hi-Z 00H Hi-Z
Enable SO to output
70H Hi-Z
80H Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RY/
(EBSY)
Disable SO to output
Status during AAI
RY/
Status during AAI
(DBSY)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 8/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
