ESMT
F25L04UA
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
(wrap-around) of the address space, i.e. for 4 Mbit density, once
the data from address location 7FFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
03H, followed by address bits [A23-A0]. CE must remain active
low for the duration of the Read cycle. See Figure 4 for the Read
sequence.
CE
MODE3
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
70
SCK MODE1
ADD.
MSB
03
ADD.
ADD.
SI
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOU T
HIGH IMPENANCE
SO
DOUT
MSB
Figure 4 : READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.2 8/25
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
