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EN25B16-100VC 参数 Datasheet PDF下载

EN25B16-100VC图片预览
型号: EN25B16-100VC
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash Memory,]
分类和应用:
文件页数/大小: 37 页 / 474 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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EN25B16  
Table 3b. Protected Area Sizes- Top Boot Sector Organization  
Status Register  
Content  
Memory Content  
Addresses  
Density(KB)  
BP2  
Bit  
0
BP1  
Bit  
0
BP0  
Bit  
0
Protect Sectors  
Portion  
None  
Sector 35  
None  
None  
4KB  
None  
0
0
0
1
1
1
1
0
1
1FF000h-1FFFFFh  
1FE000h-1FFFFFh  
1FC000h-1FFFFFh  
1F8000h-1FFFFFh  
1F0000h-1FFFFFh  
100000h-1FFFFFh  
000000h-1FFFFFh  
Upper 1/512  
Upper 1/256  
Upper 1/128  
Upper 1/64  
Upper 1/32  
Upper 1/2  
All  
1
0
Sector 34 to 35  
Sector 33 to 35  
Sector 32 to 35  
Sector 31 to 35  
Sector 16 to 35  
All  
8KB  
1
1
16KB  
32KB  
64KB  
1024KB  
2048KB  
0
0
0
1
1
0
1
1
Hold Function  
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the  
clocking sequence. However, taking this signal Low does not terminate any Write Status Register,  
Program or Erase cycle that is currently in progress.  
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition  
starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)  
being Low (as shown in Figure 4.).  
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with  
Serial Clock (CLK) being Low.  
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after  
Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)  
being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).  
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and  
Serial Clock (CLK) are Don’t Care.  
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the  
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment  
of entering the Hold condition.  
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the  
internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)  
High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold  
condition.  
Figure 4. Hold Condition Waveform  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.essi.com.tw  
9
Rev. E, Issue Date: 2007/06/07