ESMT
AD8256A
Pin Assignment
36
35
34
33
1
2
3
4
HPL
HPR
AGND
MCLK
PLLGND
PLLVDD
CLK_OUT
AVDD
32
31
30
5
6
7
DVDD
DGND2
DGND1
N.C.
PWMSA
DEF
SDA
SCL
SA1
SA0
ERROR
PD
29
28
27
26
25
8
9
10
11
12
SDATA0
SDATA1
SDATA2
LRCIN
Pin Description
TYPE
PIN
1
NAME
MCLK
DESCRIPTION
CHARACTERISTICS
I
Master clock input
Ground for PLL
Schmitt trigger TTL input buffer
2
PLLGND
PLLVDD
CLK_OUT
DVDD
P
3
P
Supply for PLL
(Note1)
TTL output buffer
(Note1)
4
O
P
PLL output
5
Digital Power
6
DGND2
DGND1
N.C.
P
Digital Ground2
7
P
Digital Ground1
8
No Connection
9
SDATA0
SDATA1
SDATA2
LRCIN
I
I
Serial audio data input 0
Serial audio data input 1
Serial audio data input 2
Left/Right clock input (Fs)
Bit clock input (64Fs)
Supply1 for right channel B
Right channel output1 (-)
Ground1 for right channel
Right channel output1 (+)
Supply1 for right channel A
Supply2 for right channel A
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
(Note2)
10
11
12
13
I
I
BCLK
I
14 VDDRB1
P
O
P
O
P
P
15
16
17
RB1
GNDR1
RA1
18 VDDRA1
19 VDDRA2
(Note2)
(Note2)
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.3
2/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
