ESMT
AD6255A
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GNDL
P
I
Ground for left channel
Low is USB mode, high is I2S mode
Mode selection bit 1
Mode selection bit 0
Crystal output
USB/I2S
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer
SEL1
I
SEL0
I
XO
O
I
XI
Crystal input
GND
P
O
P
I/O
I/O
I
Ground
REGO
VDD
3.3V regulator output
5V supply voltage
USB data D-
USBDM
USBDP
THEATER
USB data D+
Theater mode, high active
Volume down, low active
Volume up, low active
Power-down and mute of Class D
Error output
Schmitt trigger TTL input buffer
With internal pull-up resistor
With internal pull-up resistor
Schmitt trigger TTL input buffer
Open-Drain output
I
VOLDN
VOLUP
MUTE
I
I
O
I
ERROR
RESET
Reset signal
Schmitt trigger TTL input buffer
Note1: Must be strapped resistor 1MΩ to 3.3V(REGO) or GND. BCLK, LRCIN and PDO must be
strapped to GND. SDATAO is strapped by 1MΩ to GND when AD6255A’s volume/mute is
controlled by external button, otherwise strapped by 1MΩ to 3.3V when AD6255A is I2C slave
mode for SEL1 is logic LOW.
Absolute Maximum Ratings
Symbol
VDD
VDDL(R)
Vi
Parameter
Supply for regulator input
Min
0
Max
5.5
5.5
3.6
150
70
Units
V
Supply for Left (Right) Channel
Input Voltage
0
V
-0.3
-65
0
V
Tstg
Storage Temperature
oC
oC
V
Ta
Ambient Operating Temperature
Voltage Difference between VDDL and VDDR
Voltage Difference between VDDL(VDDR) and DVDD/AVDD
VDDL(VDDR) Power-on Voltage Ramp
-1
1
-3
3
V
0.2
V/μs
Recommended Operating Conditions
Symbol
Parameter
Typ
Units
V
VDD
Supply for regulator input
Supply for Driver Stage
Ambient Operating Temperature
4.5~5.5
3.0~5.0
0~70
VDDL(R)
Ta
V
oC
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.3 3/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
