PBM 3960/1
Differential Non-linearity
different levels for initiation of fast
Definition of Terms
current decay can be selected.
The sign outputs generate the phase
shifts, i.e., they reverse the current
direction in the phase windings.
The difference between any two
consecutive codes in the transfer curve
from the theoretical 1LSB, is differential
non-linearity
Resolution
Resolution is defined as the reciprocal of
the number of discrete steps in the DAC
output. It is directly related to the
number of switches or bits within the
DAC. For example, PBM 3960/1 has 27,
or 128, output levels and therefor has 7
bits resolution. Remember that this is
not equal to the number of microsteps
available.
Data Bus Interface
Monotonic
PBM 3960/1 is designed to be compat-
ible with 8-bit microprocessors such as
the 6800, 6801, 6803, 6808, 6809, 8051,
8085, Z80 and other popular types and
their 16/32 bit counter parts in 8 bit data
mode. The data bus interface consists of
8 data bits, write signal, chip select, and
two address pins. All inputs are TTL-
compatible (except reset). The two
address pins control data transfer to the
four internal D-type registers. Data is
transferred according to figure 10 and on
the positive edge of the write signal.
If the output of a DAC increases for
increasing digital input code, then the
DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that
increasing digital input codes will
produce an increasing analog output.
PBM 3960/1 is monotonic to 7 bits.
Linearity Error
Linearity error is the maximum deviation
from a straight line passing through the
end points of the DAC transfer
characteristic. It is measured after
adjusting for zero and full scale.
Linearity error is a parameter intrinsic to
the device and cannot be externally
adjusted.
Functional Description
Each DAC channel contains two
registers, a digital comparator, a flip flop,
and a D/A converter. A block diagram is
shown on the first page. One of the
registers stores the current level, below
which, fast current decay is initiated.
The status of the CD outputs determines
a fast or slow current decay to be used
in the driver.
Current Direction, Sign1 & Sign2
These bits are transferred from D7 when
writing in the respective DA register. A0
and A1 must be set according to the data
transfer table in figure 10.
Power Supply Sensitivity
Power supply sensitivity is a measure of
the effect of power supply changes on
the DAC full-scale output.
The digital comparator compares
each new value with the previous one
and the value for the preset level for fast
current decay. If the new value is strictly
lower than both of the others, a fast
current decay condition exists. The flip
flop sets the CD output. The CD output
is updated each time a new value is
loaded into the D/A register. The fast
current decay signals are used by the
driver circuit, PBL 3771/1, to change the
current control scheme of the output
stages. This is to avoid motor current
dragging which occurs at high stepping
rates and during the negative current
slopes, as illustrated in figure 9. Eight
Current Decay, CD1 & CD2
Settling Time
CD1 and CD2 are two active low signals
(LOW = fast current decay). CD1 is
active if the previous value of DA-Data1
is strictly larger than the new value of
DA-Data1 and the value of the level
register LEVEL1 (L61 … L41) is strictly
larger than the new value of DA-Data1.
CD1 is updated every time a new value
is loaded into DA-Data1. The logic
definition of CD1 is:
Full-scale current settling time requires
zero-to-full-scale or full-scale-to-zero
output change. Settling time is the time
required from a code transition until the
DAC output reaches within ±1/2LSB of
the final output value.
Full-scale Error
Full-scale error is a measure of the
output error between an ideal DAC and
the actual device output.
CD1 = NOT{[(D6 … D0) < (Q61 … Q01)]
AND[(D6 …D4) < (L61 … L41)]}
Output
Output
Output
Gain
error
Actual
More
than 2
bits
Less
than 2
bits
Correct
Endpoint
non-linearity
Negative
difference
Positive
difference
Offset error
Full scale Input
Input
Input
Figure 7. Errors in D/A conversion. Non-
linearity, gain and offset errors.
Figure 6. Errors in D/A conversion.
Differential non-linearity of less than 1 bit,
output is monotonic.
Figure 5. Errors in D/A conversion.
Differential non-linearity of more than 1
bit, output is non-monotonic.
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ERICSSON [ ERICSSON ]
