Preliminary
PBL 386 65/2
1
2
28 VTX
27 AGND
RRLY
TS
HP
3
26
25
24
23
RSN
DET
RINGX
BGND
TIPX
VBAT
VBAT2
AOV
4
LP
DT
5
6
25 HP
5
C1
C2
24 NC*
23 TS
6
DR
7
28-pin SSOP
VEE
REF
8
22 RRLY
21 VTX
20 AGND
19 RSN
28 pin PLCC
7
22 C3
21 VCC
20 PLD
9
8
10
SPR
9
PLC 11
10
19
PLC
PSG
LP
11
12
18 SPR
17
DT
REF
13
14
DR
16 VEE
*NC
15
NC*
* Pins must be left open.
Figure 8. Pin configuration 28 pin SSOP and 28 pin package, top view.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Active state
Tip open state
Active state
Detector is set high
Ring trip detector (active low)
Loop detector (active low)
Line voltage measurement
Loop detector (active low)
Ground key detector (active high)
Loop detector (active low)
Ground key detector (active high)
Active reverse
Active reverse
Table 1. SLIC operating states.
9
ERICSSON [ ERICSSON ]
