PBL 386 21/2
1
2
24 VTX
PTG
RRLY
HP
23 AGND
3
22
21
20
19
RSN
REF
PLC
POV
5
6
25
24
23
22
21
20
19
RINGX
BGND
NC
RINGX
BGND
TIPX
4
REF
PLC
POV
PLD
VCC
NC
24-pin SOIC
and
24-pin SSOP
5
7
TIPX
VBAT
6
28-pin PLCC
8
VBAT
VBAT2
PSG
7
18 PLD
17 VCC
16 DET
VBAT2
9
8
10
11
PSG
NC
9
10
15
C1
LP
DT
DR
11
12
14 C2
13
C3
Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.
Pin Description
Refer to figure 7.
PLCC
Symbol
PTG
RRLY
HP
Description
1
2
3
4
5
Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB.
Ring Relay driver output. The relay coil may be connected to maximum +14V.
Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX.
No internal Connection.
NC
RINGX
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
6
7
BGND
TIPX
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
8
VBAT
VBAT2
PSG
Battery supply Voltage. Negative with respect to GND.
9
An optional second (2) Battery Voltage connects to this pin via an external diode.
10
Programmable Saturation Guard. The resistive part of the DC feed characteristic is not used for
PBL 386 21/2, RSG = 0 Ω.
11
12
13
NC
LP
DT
No internal Connection.
Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
14
DR
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
8
ERICSSON [ ERICSSON ]
