PBL 3762A/2, /4
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
VCC current, ICC
Active state
C1, C2 = 0, 1
On-hook
5.1
2.0
3.3
8.0
3.5
5.2
mA
mA
mA
VEE current, IEE
Bat current, IBat
V
Power supply rejection ratios
VCC to 2- or 4-wire port
VEE to 2- or 4-wire port
VBat to 2- or 4-wire port
VBat to 2- or 4-wire port
Active State
C1, C2 = 0, 1
50 Hz < f< 3400 Hz, Vn = 100mVrms
Vn = 2VPP, Note 11
43
45
45
45
45
dB
dB
dB
dB
40
40
40
Temperature Guard
Junction threshold temperature, TJG
Thermal resistance
28-pin PLCC, θRJP28plcc
150
13
°C
Junction to terminals 3, 6, 10, 17, 24
connected together, Note 12
°C/W
°C/W
22-pin PDIP, θRJP22dip
33
E0
DET
10%
90%
tDHL
tDHL
Figure 7. Detector output delay time.
Notes
α
RSN = receive current gain, nominally = -1000 (current
defined as positive flowing into the receivesumm-ing
node, RSN, and when flowing from tip to ring).
1. The overload level is specified at the two-wire port with
the signal source at the four-wire receive port.
2. The two-wire impedance is programmable by selection of
external component values according to:
3. Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing RT into
two equal halves and connecting a capacitor from the
common point to ground. For RT = 560 kΩ this capacitor
would be approximately 30 pF. Increasing CHP to 0.033 µF
improves low frequency return loss.
ZTRX = ZT/|G2-4 •α RSN| where:
ZTRX = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
G2-4 = transmit gain, nominally = 1
7
ERICSSON [ ERICSSON ]
