PBD 3517/1
determined by VSS voltage and motor
data, the L/R time-constant.
STEP — Stepping pulse
Functional Description
One step is generated for each negative
edge of the STEP signal. In half-step
mode, two pulses will be required to move
one full step. Notice the set up time, ts, of
DIR and HSM signals. These signals
must be latched during the negative edge
of STEP, see timing diagram, figure 3.
The circuit, PBD 3517/1, is a high
perform-ance motor driver, intended to
drive a stepper motor in a unipolar, bilevel
way. Bilevel means that during the first
time after a phase shift, the voltage
across the motor is increased to a second
voltage supply, VSS, in order to obtain a
more-rapid rise of current, see figure 11.
The current starts to rise toward a
value which is many times greater than
the rated winding current. This compen-
sates for the loss in drive current and loss
of torque due to the back emf of the
motor.
In a low-voltage system, where high
motor performance is needed, it is also
possible to double the motor voltage by
adding a few external components, see
figure 14.
The time the circuit applies the higher
voltage to the motor is controlled by a
monostable flip-flop and determined by
the timing components RT and CT.
The circuit can also drive a motor in
traditional unipolar way.
DIR — Direction
DIR determines in which direction steps
will be taken. Actual direction depends on
motor and motor connections. DIR can be
changed at any time, but not simultan-
eously with STEP, see timing diagram,
figure 3.
HSM determines whether the motor will
be controlled in full-step or half-step
mode. When pulled low, a step-pulse will
correspond to a half step of the motor.
HSM can be changed at any time, but not
simultaneously with STEP, see timing
diagram, figure 3.
An inhibit input (INH) is used to switch
off the current completely.
Logic inputs
After a short time, tOn, set by the
monostable, the bilevel output is switched
off and the winding current flows from the
All inputs are LS-TTL compatible. If any
of the logic inputs are left open, the
circuit will accept it as a HIGH level. PBD
3517/1 contains all phase logic
necessary to control the motor in a
proper way.
VMM supply, which is chosen for rated
winding current. How long this time must
be to give any increase in performance is
V
V
SS
D3
MM
+ 5V
+
+
+
PBD 3517/1
D2
D1
C
3
C
4
C
5
VCC
16
VSS
15
V
CC
R11
R10
PQR
RC 12
13 LA
14 LB
Mono
F - F
CMOS, TTL-LS
Input / Output-Device
MOTOR
R
T
C
T
R9 R8
STEP
DIR
7
6
STEP
D3-D6
PA
PB
Phase
Logic
1
2
PB2
PB1
CW / CCW
HSM 10
INH 11
HALF / FULL STEP
5
4
PA2
PA1
NORMAL /INHIBIT
(Optional Sensor)
OA
OB
9
8
D3-D6 are
UF 4001 or
BYV 27
3
GND
Figure 14.
Typical
<
GND
trr 100 ns
GND (V )
CC
GND (V ,V )
MM SS
application.
VMM
+ 5V
+
+
R1
PBD 3517/1
D1
C3
C4
VCC
VSS
15
16
VCC
R10
PQR
Q1
Q3
C1
RC 12
13 LA
14 LB
Mono
F - F
CMOS, TTL-LS
Input / Output-Device
RT CT
R9 R8
R2
STEP
DIR
7
6
STEP
1/2 MOTOR
R13
Equal to
Phase A
PA
PB
Phase
Logic
1
2
PB2
PB1
CW / CCW
R12
HSM 10
INH 11
HALF / FULL STEP
R4
R5
5
4
PA2
PA1
Q5
NORMAL /INHIBIT
(Optional Sensor)
OA
OB
9
8
Q6
Figure 15. Voltage
doubling with
external
3
GND
GND
GND (VCC
)
GND (VMM,VSS
)
transistors.
6
ERICSSON [ ERICSSON ]
