4. FUNCTIONS
4. FUNCTIONS
4.1 Power Supply
This LSI has three power supply circuits and a common ground. The power supply circuits consist of HVDD
(3.3 V) for USB I/O, IDE I/O, and TEST I/O; CVDD (3.3 V to 1.8 V) for CPU I/F I/O; and LVDD (1.8 V) for
internal circuits. (See Fig.4.1)
LVDD
1.8V
HVDD
3.3V
H_SIE
D_SIE
HTM
DTM
CPU
USB
I
O
CPU
-I/F
FIFO
IDE
-I/F
IO
TEST
IO
CVDD
1.8V to 3.3V
IDE
Fig.4.1 S1R72C05 power supplies
Given below are the sequences for turning the power supplies on and off.
This LSI will not operate with only some of the power supplies turned on or off. The following restrictions
apply to the sequence for turning the CVDD/HVDD I/O power supplies and LVDD internal power supply on or
off. There are no restrictions on the sequence for turning the CVDD and HVDD power supplies on or off.
•
•
The LVDD must be turned on before turning on the CVDD and HVDD power supplies.
The CVDD and HVDD power supplies must be turned off before turning off the LVDD.
If adherence to this sequence is not possible for reasons related to power supply circuit characteristics or load,
the CVDD or HVDD must be on for no longer than 1 second while the LVDD is off.
4.2 Boundary Scan
Boundary scanning (JTAG) may be used when the TEST terminal is set to “Low” (default). Boundary
scanning consists of a BSR (Boundary Scan Register) conforming to the JTAG (IEEE 1149.1) specifications, a
connecting scan path, and a TAP controller. Boundary scan connection information may be provided in BSDL
format.
4.2.1 Instructions Supported
This LSI has a JTAG instruction bit width of 4 bits and supports the following JTAG instructions.
4
EPSON
S1R72C05*** Data Sheet (Rev.1.00)
EPSON [ EPSON COMPANY ]
