EM48BM1684LBC
AC Operating Test Conditions
(VDD=1.8V)
Item
Conditions
0.5*VDDQ
Output Reference Level
Output Load
See diagram as below
0.9*VDDQ/0.2
1ns/1ns
Input Signal Level
Transition Time of Input Signals
Input Reference Level
0.5*VDDQ
AC Operating Test Characteristics
(VDD=1.8V)
-6
-75
Max
Symbol Parameter
Units
Min
6
Max
Min
7.5
-
tCK
tAC
tCH
tCL
tOH
Clock Cycle Time
CL=3
CL=3
-
-
ns
ns
ns
ns
ns
ns
Access Time form CLK
CLK High Level Width
CLK Low Level Width
Data-out Hold Time
-
5.4
5.4
2
-
2.5
2.5
2.5
-
-
2
-
-
CL=3
CL=3
2.5
-
-
-
Data-out High Impedance Time
(Note 5)
5.4
5.4
tHZ
tLZ
tIH
tIS
Data-out Low Impedance Time
Input Hold Time
1
-
-
-
1
-
-
-
ns
ns
ns
1
1
Input Setup Time
1.5
1.5
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not
referenced to output voltage levels.
Jun. 2012
www.eorex.com
9/20
EOREX [ EOREX CORPORATION ]
