EM484M3244LBB
128Mb (1M×4Bank×32)
Mobile Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• JEDEC Standard 1.8V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8 or
Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of the
System Clock
• Support Deep Power Down Mode
• Partial Array Self Refresh (PASR)
• Auto Temperature Compensated Self Refresh
(Auto TCSR)
The EM484M3244LBB is Mobile Synchronous
Dynamic Random Access Memory (Mobile
SDRAM) organized as 1Meg words x 4 banks by
32 bits. All inputs and outputs are synchronized
with the positive edge of the clock.
The 128Mb Mobile SDRAM uses synchronized
pipelined architecture to achieve high speed data
transfer rates and is designed to operate at 1.8V
ultra low power memory system. It also provides
auto refresh with deep power saving / down mode.
The data paths are internally pipelined to achieve
very high bandwidth. All inputs and outputs voltage
levels are compatible with LVCMOS.
Available packages: TFBGA-90B (13mmx8mm).
• Driver Strength (DS)
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM484M3244LBB-75F
4M X 32
133MHz @CL3
TFBGA -90B
Commercial Free
EM484M3244LBB-6F
EM484M3244LBB-75FE
EM484M3244LBB-6FE
4M X 32
4M X 32
4M X 32
166MHz @CL3
133MHz @CL3
166MHz @CL3
TFBGA -90B
TFBGA -90B
TFBGA -90B
Commercial Free
Extend
Extend
Free
Free
Jul. 2010
www.eorex.com
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EOREX [ EOREX CORPORATION ]
