EM44DM0888LBA
Recommended DC Operating Conditions
(VDD=1.8V 0.1V)
-187(1066) -25(800)
Symbol
Parameter
Test Conditions
Units
Max
IOUT = 0mA
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRC = tRC (IDD)
tRAS = tRASmin(IDD), tRCD = tRCD(IDD)
CKE=HIGH
I
DD1
Operating Current (Note 1)
102
85
mA
CS=HIGH between valid commands
Address bus inputs are SWITCHING
Data pattern is same as IDD4W
All banks idle
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Data bus inputs are FLOATING
All banks idle
tCK = tCK(IDD), CKE is HIGH, CS is HIGH
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
All banks open
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Data bus inputs are FLOATING
All banks open
Precharge Standby Current
in Power Down Mode
I
I
DD2P
DD2N
10
48
10
40
mA
mA
Precharge Standby Current
in NON-power down mode
All banks idle
Active Standby Current in
Power Down Mode (A12=0)
Active Standby Current in
Power Down Mode (A12=1)
I
I
DD3P
DD3P
36
11
30
10
mA
mA
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
All banks open, Continuous burst writes
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are SWITCHING
Data bus inputs are SWITCHING
tCK = tCK(IDD)
Active Standby Current
in Non-power Down Mode
I
DD3N
60
50
mA
mA
I
I
DD4W
DD4R
144
144
120
120
Operating Current (Burst
Mode) (Note 2)
Refresh command at every tRFC(IDD) interval
CKE is HIGH, CS is HIGH between valid
commands
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
CK and CK at 0 V, CKE 0.2 V
Other control and address bus inputs are
FLOATING, Data bus inputs are FLOATING
All bank interleaving reads
I
I
DD5
DD6
Refresh Current (Note 3)
Self Refresh Current
210
9
175
9
mA
mA
IOUT = 0mA, BL = 4, CL = CL(IDD)
AL = tRCD(IDD) - 1 x tCK(IDD)
tCK = tCK(IDD), tRC = tRC(IDD)
tRRD = tRRD(IDD), tFAW = tFAW(IDD)
tRCD = 1 x tCK(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are STABLE during
DESELECTs
I
DD7
Operating Current
300
250
mA
Data pattern is same as IDD4R
*All voltages referenced to VSS.
Note 1: IDD1 depends on output loading and cycle rates (CL=CLmin, AL=0)
Note 2: IDD4 depends on output loading and cycle rates Input signals SWITCHING
Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Feb. 2012
8/29
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EOREX [ EOREX CORPORATION ]
