EM44CM0884LBA
Recommended DC Operating Conditions
(VDD=1.8V±0.1V)
-3(667)
-25(800)
Symbol
Parameter
Test Conditions
Units
mA
Max
IOUT = 0mA
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRC = tRC (IDD)
tRAS = tRASmin(IDD), tRCD = tRCD(IDD)
CKE=HIGH
IDD1
Operating Current (Note 1)
75
85
CS=HIGH between valid commands
Address bus inputs are SWITCHING
Data pattern is same as IDD4W
All banks idle
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Data bus inputs are FLOATING
All banks idle
tCK = tCK(IDD), CKE is HIGH, CS is HIGH
Other control and address bus inputs are
SWITCHING
Precharge Standby Current
in Power Down Mode
IDD2P
IDD2N
6
6
mA
mA
Precharge Standby Current
in NON-power down mode
All banks idle
40
45
Data bus inputs are SWITCHING
All banks open
Active Standby Current in
Power Down Mode (A12=0)
Active Standby Current in
IDD3P
IDD3P
25
11
30
11
mA
mA
tCK = tCK(IDD), CKE is LOW
Other control and address bus inputs are
STABLE
Power Down Mode (A12=1) Data bus inputs are FLOATING
All banks open
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Other control and address bus inputs are
SWITCHING
Active Standby Current
in Non-power Down Mode
IDD3N
35
45
mA
mA
Data bus inputs are SWITCHING
All banks open, Continuous burst writes
BL = 4, CL = CL(IDD), AL = 0
tCK = tCK(IDD), tRAS = tRASmax(IDD)
tRP = tRP(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are SWITCHING
Data bus inputs are SWITCHING
tCK = tCK(IDD)
IDD4W
IDD4R
100
100
120
115
Operating Current (Burst
Mode) (Note 2)
Refresh command at every tRFC(IDD) interval
CKE is HIGH, CS is HIGH between valid
commands
Other control and address bus inputs are
SWITCHING
Data bus inputs are SWITCHING
CK and CK at 0 V, CKE 0.2 V
Other control and address bus inputs are
FLOATING, Data bus inputs are FLOATING
All bank interleaving reads
IDD5
IDD6
Refresh Current (Note 3)
Self Refresh Current
140
6
155
6
mA
mA
IOUT = 0mA, BL = 4, CL = CL(IDD)
AL = tRCD(IDD) - 1 x tCK(IDD)
tCK = tCK(IDD), tRC = tRC(IDD)
tRRD = tRRD(IDD), tFAW = tFAW(IDD)
tRCD = 1 x tCK(IDD), CKE is HIGH
CS is HIGH between valid commands
Address bus inputs are STABLE during
DESELECTs
IDD7
Operating Current
200
220
mA
Data pattern is same as IDD4R
*All voltages referenced to VSS.
Note 1: IDD1 depends on output loading and cycle rates. (CL=CLmin, AL=0)
Note 2: IDD4 depends on output loading and cycle rates. Input signals SWITCHING
Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Dec. 2014
7/28
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EOREX [ EOREX CORPORATION ]
