EM42AM3284LBB
512Mb (4M×4Bank×32)
Double DATA RATE SDRAM
Features
Description
• Internal Double-Date-Rate architecture with 2
accesses per clock cycle.
• JEDEC standard 1.8V ±0.1V VDD/VDDQ
• 1.8V LV-COMS compatible I/O
The EM42AM3284LBB is a Double Data Rate
Synchronous DRAM fabricated with ultra-high
performance
CMOS
process
containing
536,870,912 bits which organized as 4Meg words x
4 banks by 32 bits.
• Burst Length (B/L) of 2, 4, 8 or 16
• 3 Clock read latency
• Bi-directional, intermittent data strobe (DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• No DLL; CK to DQS is not synchronized
• Deep power down mode
The 512Mb DDR SDRAM uses double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the data for both rising and falling edges
of the system clock. It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages: TFBGA-90B (13mmx8mm).
• Partial Array Self-Refresh (PASR)
• Auto Temperature Compensated Self-Refresh
(TCSR) by built-in temperature sensor
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Ordering Information
Part No
Organization
Max. Freq
Package
Grade
Pb
EM42AM3284LBB-75F
16M X 32
133MHz/DDR266 @CL3 TFBGA-90B Commercial Free
166MHz/DDR333 @CL3 TFBGA-90B Commercial Free
133MHz/DDR266 @CL3 TFBGA-90B Extend temp. Free
166MHz/DDR333 @CL3 TFBGA-90B Extend temp. Free
EM42AM3284LBB-6F
EM42AM3284LBB-75FE
EM42AM3284LBB-6FE
16M X 32
16M X 32
16M X 32
Jul. 2010
www.eorex.com
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EOREX [ EOREX CORPORATION ]
