eorex
EM428M1644RTA
AC Operating Test Conditions
(VDD=2.5V 0.2V, TA=0°C ~70°C)
Item
Conditions
1.25V/1.25V
Output Reference Level
Output Load
See diagram as below
VREF+0.31V/ VREF-0.31V
1ns
Input Signal Level
Transition Time of Input Signals
Input Reference Level
VDDQ/2
AC Operating Test Characteristics
(VDD=2.5V 0.2V, TA=0°C ~70°C)
-5
-6
-7.5
Min. Max.
Symbol
Parameter
Units
Min.
-0.65
-0.55
0.45
-
Max.
0.65
0.55
0.55
-
Min.
-0.7
-0.6
0.45
7.5
6
Max.
0.7
0.6
0.55
12
tDQCK
tDQSCK
tCL,tCH
DQ output access from CLK,/CLK
DQS output access from CLK,/CLK
CL low/high level width
CL=2
-0.75 0.75
-0.75 0.75
ns
ns
tCK
ns
ns
ns
ns
0.45
10
0.55
12
12
-
tCK
Clock Cycle Time
CL=2.5
CL=3
6
12
12
7.5
-
5
8
-
-
tDH,tDS DQ and DM hold/setup time
0.4
0.45
0.5
DQ and DM input pulse width for
each input
Data out high/low impedance time
from CLK,/CLK
DQS-DQ skew for associated DQ
signal
Write command to first latching DQS
transition
tDIPW
tHZ,tLZ
tDQSQ
tDQSS
1.75
-0.7
1.75
-0.7
1.75
ns
ns
ns
tCK
tCK
tCK
0.7
0.7
-0.75 0.75
0.5
0.4
0.45
0.75 1.25
0.7
1.25
0.75
1.25
tDSL,tDS
DQS input valid window
0.35
0.35
0.35
H
Mode Register Set command cycle
time
tMRD
2
0
21
0
2
0
tWPRES Write Preamble setup time
ns
tWPST
tIH,tIS
tRPRE
Write Preamble
0.4
0.9
0.6
1.1
0.4
0.9
0.6
1.1
0.4
0.9
0.6
1.1
tCK
Address/control input hold/setup
time
0.7
0.8
1.0
ns
Read Preamble
tCK
Apr. 2007
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