EN6347QI
Pin Assignments (Top View)
Figure 2: Typical Application Schematic (PWM mode)
Ordering Information
Temp Rating
(°C)
Part Number
EN6347QI
Package
38-pin QFN T&R
38-pin QFN T&R
Figure 3: Pinout Diagram (Top View)
NOTE: All pins must be soldered to PCB.
-40 to +85
-40 to +85
EN6347QI3
EN6347QI-E
QFN Evaluation Board
Pin Description
PIN
NAME
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
1-2, 12,
34-38
NC(SW)
3-4,
NO CONNECT – These pins may be internally connected. Do not connect to each other or
to any other electrical signal. Failure to follow this guideline may result in device damage.
NC
22-25
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 13-15.
5-11
13-18
19-21
VOUT
PGND
PVIN
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 16-18.
Dual function pin providing LLM Enable and External Clock Synchronization (see
Application Section). At static Logic HIGH, device will allow automatic engagement of light
load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this
pin will synchronize the internal switching frequency to the external signal. If this pin is left
floating, it will pull to a static logic high, enabling LLM.
26
LLM/SYNC
Input Enable. Applying logic high enables the output and initiates a soft-start. Applying
logic low disables the output.
27
28
29
30
ENABLE
POK
Power OK is an open drain transistor used for power system state indication. POK is logic
high when VOUT is within -10% of VOUT nominal.
Programmable LLM engage resistor to AGND allows for adjustment of load current at which
Light-Load Mode engages. Can be left open for PWM only operation.
RLLM
SS
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
31
VFB
32
33
AGND
AVIN
Analog Ground. This is the controller ground return. Connect to a quiet ground.
Input power supply for the controller. Connect to input voltage at a quiet point.
Device thermal pad to be connected to the system GND plane. See Layout
Recommendations section.
39
PGND
@Enpirion 2011 all rights reserved, E&OE
2
www.enpirion.com
05991
10/04/2011
Rev: B
ENPIRION [ ENPIRION, INC. ]
