EN5364QI
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
Input Voltage
SYMBOL
VIN
COMMENTS
MIN
2.375
TYP
MAX UNITS
6.6
V
Under Voltage Lock out
threshold
VUVLOR
VUVLOF
VIN Increasing
VIN Decreasing
2.2
2.1
V
Shut-Down Supply
Current
IS
ENABLE=0V
250
μA
V
2.375V ≤ VIN ≤ 6.6V,
Feedback Pin Voltage
VFB
IFB
0.588
-5
0.600
0.612
5
I
LOAD = 1A; TA = 25°C
Feedback Pin Input Leakage
Current1
nA
Line Regulation
Load Regulation
Temperature Regulation
2.375V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 6A
ΔVOUT_TEMP -40°C ≤ TEMP ≤ 85°C
Measured from when VIN ≥ VUVLOR
0.035
−0.04
0.001
%/V
%/A
%/°C
ΔVOUT_LINE
ΔVOUT_LOAD
CSS x
TRISE
& ENABLE pin crosses logic high
threshold. (4.7nF ≤ CSS ≤ 100nF)
4.7nF ≤ CSS ≤ 100nF
VOUT Rise Time
65kΩ
Rise Time Accuracy1
Output Dropout
Voltage1
-25
6
+25
%
ΔTRISE
mV
mΩ
VDO
RDO
VINMIN – VOUT at Full Load
Input to Output Resistance
240
40
480
80
Resistance1
Maximum Continuous
Output Current2
Current Limit Threshold
ENABLE pin:
IOUT_MAX_CONT
IOCP
A
A
OCP_ADJ floating
2.375V ≤ VIN ≤ 6.6V
10.5
Disable Threshold
Enable Threshold
VDISABLE
VENABLE
ENABLE pin logic low
1.0
1.30
V
ENABLE pin logic high
Time for device to re-enable after
a falling edge on ENABLE pin
1.10
tENLO
ENABLE Lock-out time
2
ms
ENABLE Pin Input
Current
IENABLE
FSWITCH
FPLL_LOCK
VIN = 5.5V
50
4
μA
Switching Frequency
External S_IN Clock
Frequency Lock Range
S_IN Threshold – Low
S_IN Threshold – High
S_OUT Threshold – Low
S_OUT Threshold – High
S_IN Duty Cycle for
External Synchronization1
S_IN Duty Cycle for
Parallel Operation1
Free Running frequency
Frequency Range of S_IN
Input Clock
S_IN Clock low level
S_IN Clock high level
S_OUT Clock low level
S_OUT Clock high level
MHz
MHz
3.6
1.8
4.4
VS_IN_LO
VS_IN_HI
VS_OUT_LO
VS_OUT_HI
0.8
2.5
0.5
V
V
V
V
1.8
20
SYDC_SYNC M/S Pin Float or Low
80
90
%
%
SYDC_PWM M/S Pin High
10
20
ns
°
Delay in ns / kΩ
2
3
Phase Delay vs. S_Delay
Resistor value
ΦDEL
Delay in phase angle / kΩ -
@ 4MHz switching frequency
Phase delay programmable via
resistor connected from S_Delay
to AGND.
Phase Delay between
S_IN and S_OUT1
150
ns
ΦDEL
©Enpirion 2009 all rights reserved, E&OE
5
www.enpirion.com
03544
8/21/2009
Rev:B
ENPIRION [ ENPIRION, INC. ]
