Rev 1.0 – July 2005
EN5330
PWM operation resumes and POK returns to its high
state.
outside the package at one point through a low-
impedance trace. The connection should be made such
that the impedance between the connection point and
the AGND pad on the package is minimized. Since
the internal voltage sensing circuit is based on AGND,
the connection of the two grounds should also be
made such that the best voltage regulation can be
achieved. The soft-start capacitor, the voltage
programming resistors, and any other external control
component should be tied to AGND.
Thermal Overload Protection
Thermal shutdown will disable operation once the
Junction temperature exceeds approximately 160ºC.
Once the junction temperature drops by approx 25ºC,
the converter will re-start with a normal soft-start.
Low Input Voltage Operation
Circuitry is provided to ensure that when the input
voltage is below the specified voltage range, the
operation of the converter is controlled and
The placement of the input decoupling capacitors
between PVIN and PGND is very critical. These
predictable. Circuits for hysteresis, input de-glitch and components should be placed such that they have the
output leading edge blanking are included to ensure
high noise immunity and prevent false tripping.
lowest inductance traces to PVIN and PGND.
There are two thermal pads underneath the device.
The centrally located pad is PGND, and, depending on
the number of layers of the PC board, it needs to be
connected to a thermal plane in order to conduct heat
away from the device. Note that if any of the thermal
Compensation
The EN5330 is internally compensated through the
use of a type 3 compensation network and is
optimized for use with about 50µF of output
capacitance and will provide excellent loop bandwidth planes is also connected to AGND, the impedance
and transient performance for most applications. (See
the section on Capacitor Selection for details on
recommended capacitor types.) In some cases
modifications to the compensation may be required.
For more information, contact Enpirion Applications
Engineering support.
between this point and the GND connection of the
load needs to be minimized in order to get the best
possible load regulation. The pad opposite the VOUT
pins is connected to VOUT. This VOUT pad should be
connected to a top layer copper area as large as
possible to conduct more heat away from the package.
This will also help minimize the trace length to the
output filter caps.
Layout Considerations
The EN5330 Layout Guidelines application note
provides more details on specific layout
recommendations for this part. The following are
general layout guidelines to consider.
Pin 19 is a connected to a noisy internal node and is
brought out for test purposes only. Keep all sensitive
signal traces as far as possible from this pin. Ideally,
on the top layer there should be no traces or vias
underneath the package between this pin and the VOUT
thermal pad.
The CMOS chip inside the EN5330 has two grounds:
AGND for the controller, and PGND for the power
stage. These two grounds need to be connected
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