EM621FU16BU Series
Low Power, 128Kx16 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
3)
VTM
2)
R1
Input Pulse Level : 0.4V to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
1)
Output Load (See right) : CL = 100pF + 1 TTL (70ns)
1)
2)
CL = 30pF + 1 TTL (45ns/55ns)
R2
1)
CL
1. Including scope and Jig capacitance
2. R =3070 ohm,
R =3150 ohm
2
1
3. V =2.8V
TM
4. CL = 5pF + 1 TTL (measurement with t , t , t
, t
, t
)
LZ HZ OLZ OHZ WHZ
o
o
READ CYCLE (V =2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
Max
55ns
Max
70ns
Min Max
Symbol
Parameter
Unit
Min
Min
Read cycle time
tRC
tAA
45
-
-
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
45
45
25
45
-
-
-
-
55
55
25
55
-
70
70
35
70
-
Chip select to output
tCO
tOE
tBA
-
-
Output enable to valid output
UB, LB access time
-
-
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ
10
5
10
10
5
10
10
5
tBLZ
tOLZ
tHZ
-
-
-
5
-
-
-
0
20
15
15
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
0
0
0
0
0
0
10
10
10
o
o
WRITE CYCLE (V =2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
Parameter
Write cycle time
A
45ns
Max
55ns
Max
70ns
Unit
Symbol
Min
Min
Min
Max
tWC
tCW
tAS
45
-
-
55
-
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
60
0
-
-
-
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
35
0
-
45
45
40
0
-
60
60
50
0
-
-
-
-
-
-
-
Write recovery time
-
-
-
Write to ouput high-Z
0
15
0
20
0
20
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
25
0
30
0
-
-
-
-
-
-
tOW
5
5
5
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
