EM641FT8
Low Power, 512Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (WE Controlled, OE LOW)
tWC
Address
4)
tWR
2)
tCW
CS
tAW
3)
1)
tAS
tWP
WE
tDH
tDW
High-Z
High-Z
Data in
Data Valid
tWHZ
Data Undefined
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among
CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high.
The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
