EM620FV8BT Series
Low Power, 256Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=V , CS2=WE=V )
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )
IH
tRC
Address
tAA
tCO1,2
tOH
CS1
CS2
tHZ1,2
tOE
OE
tOHZ
tOLZ
High-Z
Data Out
Data Valid
tWHZ
tLZ1,2
NOTES (READ CYCLE)
1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.
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