EM640FP8 Series
merging Memory & Logic Solutions Inc.
Low Power, 512Kx8 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.2V to VCC-0.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 0.9V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=1.8V
READ CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC)
70ns
Symbol
Parameter
Read cycle time
Unit
Max
Min
tRC
tAA
tco1, tco2
tOE
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2
tOHZ
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
70
70
35
-
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
10
5
-
0
25
25
-
0
tOH
10
WRITE CYCLE (Vcc =1.65 to 2.2V, Gnd = 0V, TA = -40oC to +85oC)
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
tWC
tCW1, tCW2
tAs
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
60
0
-
-
Address valid to end of write
Write pulse width
tAW
60
55
0
-
tWP
-
Write recovery time
tWR
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tWHZ
tDW
0
25
30
0
tDH
-
-
tOW
5
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
