EM620FV8BS Series
Low Power, 256Kx8 SRAM
3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
VTM
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF + 1 TTL (70ns)
2)
R2
CL1)
CL1) = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R1=3070 ohm
3. VTM=2.8V
,
R2=3150 ohm
4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ1,2, tOLZ, tOHZ, tWHZ
)
o
o
READ CYCLE (V = 2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
55ns
70ns
Max
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Read cycle time
tRC
tAA
tCO1, tCO2
tOE
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2
tOHZ
45
-
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
45
45
25
-
-
-
55
55
25
-
-
-
70
70
35
-
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
-
10
5
10
5
10
5
-
-
-
0
20
15
-
0
20
20
-
0
25
25
-
0
0
0
tOH
10
10
10
o
o
WRITE CYCLE (V = 2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
Parameter
Write cycle time
A
45ns
55ns
70ns
Unit
Symbol
Min
Max
Min
Max
Min
Max
tWC
tCW1, tCW2
tAS
45
-
-
55
-
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
60
0
-
-
-
-
Address valid to end of write
Write pulse width
tAW
45
35
0
-
45
40
0
-
60
50
0
-
tWP
-
-
-
Write recovery time
tWR
-
-
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tWHZ
tDW
0
15
0
20
0
20
25
0
25
0
30
0
tDH
-
-
-
-
-
-
tOW
5
5
5
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
