EM84502
PS/2 MOUSE CONTROLLER
Bit
Function
1
Start bit ( always 0 )
Data bits ( D0 - D7 )
Parity bit ( odd parity )
Stop bit ( always 1 )
2-9
10
11
iv). Data Output ( data from EM84502 to system ):
If CLK is low ( inhibit status ) , data is no transmission.
If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the system
and no transmission are started by EM84502 until CLK and DATA both high. If CLK and DATA are both
high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge
of CLK. During transmission, EM84502 check for line contention by checking for an inactive level on CLK
at intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84502
output after EM84502 has started a transmission. If this occurs before the rising edge of the tenth clock,
EM84502 internal store its data in its buffer and returns DATA and CLK to an active level. If the contention
does not occur by the tenth clock, the transmission is complete.
Following a transmission, the system inhibits EM84502 by holding CLK low until it can service the input
or until the system receives a request to send a response from EM84502.
v). Data Input ( from system to EM84502 ):
System first check if EM84502 is transmitting data. If EM84502 is transmitting, the system can override
the output forcing CLK to an inactive level prior to the tenth clock. If EM84502 transmission is beyond
the tenth clock, the system receives the data. If EM84502 is not transmitting or if the system choose to
override the output, the system force CLK to an inactive level for a period of not less than 100µ sec while
preparing for output. When the system is ready to output start bit (0), it allows CLK go to active level. If
request-to-send is detected, EM84502 clocks 11 bits. Following the tenth clock EM84502 checks for
an active level on the DATA line, and if found, force DATA low , and clock once more. If occurs framing
error, EM84502 continue to clock until DATA is high, then clocks the line control bit and request a
Resend. When the system sends out a command or data transmission that requires a response, the system
waits for EM84502 to response before sending its next output.
D). PS/2 Mouse Error Handling:
i). A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.
ii). If two invalid input are received in succession, an error code of hex FC send to the system.
iii). The counter accumulators are cleared after receiving any command except “Resend”.
iv). EM84501 receives a Resend command ( FE ), it transmit its last packet of data.
v). In the stream mode “Resend” is received by EM84502 following a 3-byte data packet transmission
to the system. EM84502 resend the 3-byte data packet prior to clearing the counter.
vi). A response is sent within 25 ms if
6.18.1998
* This specification are subject to be changed without notice.
4
ELAN [ ELAN MICROELECTRONICS CORP ]
