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EM78P451SWM 参数 Datasheet PDF下载

EM78P451SWM图片预览
型号: EM78P451SWM
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微控制器 [8-Bit Microcontroller with OTP ROM]
分类和应用: 微控制器光电二极管可编程只读存储器OTP只读存储器时钟
文件页数/大小: 54 页 / 421 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P451S  
8-Bit Microcontroller with OTP ROM  
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,  
"JMP" allows jump to any location on one page.  
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into  
the stack. Thus, the subroutine entry address can be located anywhere within a  
page  
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents  
at the top of stack.  
"MOV R2, A" allows the loading of an address from the "A" register to the lower 8  
bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared.  
"ADD R2, A" allows a relative address be added to the current PC, and the ninth  
and tenth bits of PC are cleared.  
Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅)  
(except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared.  
Thus, the computed jump is limited to the first 256 locations of any program page.  
"TBL" allows a relative address be added to the current PC (R2+AR2), and  
contents of the ninth and tenth bits (A8~A9) of PC are not changed. Thus, the  
computed jump can be on the second (or third, 4th) 256 locations on one program  
page.  
In case of EM78P451S, the most significant bits (A10~A11) will be loaded with the  
contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP",  
"CALL", or any other instructions which writes to R2.  
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction  
that would change the contents R2. Such instruction will need one more  
instruction cycle.  
R3  
000H  
001H  
002H  
A11 A10 A9 A8  
A7  
~
A0  
Hardware Vector  
Software Vector  
CALL  
RET  
RETL  
On-chip Program  
Memory  
RETI  
00 PAGE0 0000~03FF  
Stack Level 1  
Stack Level 2  
Stack Level 3  
Stack Level 4  
Stack Level 5  
01 PAGE1 0400~07FF  
10 PAGE2 0800~0BFF  
11 PAGE3 0C00~0FFF  
Reset Vector  
FFFH  
Fig. 3 Program Counter Organization  
Product Specification (V1.0) 06.01.2004  
5  
(This specification is subject to change without further notice)