EM78P153S
OTP ROM
4. FUNCTION DESCRIPTION
OSCO
OSCI
/RESET
TCC /INT
WDT timer
Oscillator/Timing
Control
ROM
R2
Stack
ALU
Prescaler
Interrupt
Instruction
Register
Built-in
OSC
RAM
R4
Controller
R3
R1(TCC)
Instruction
Decoder
ACC
DATA & CONTROL BUS
P60
P61
P62/TCC
P63//REST
IOC6
R6
IOC5
R6
P50
P51
P52
P53
I/O
PORT 6
I/O
PORT 5
P64/OSCO
P65/OSCI
P66
P67
Fig. 2 Functional block diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer.
Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register
(R4).
2. R1 (Time Clock /Counter)
• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or
by the instruction cycle clock.
• Writable and readable as any other registers.
• Defined by resetting PAB (CONT-3).
• The prescaler is assigned to TCC if the PAB bit (CONT-3) is reset.
• The contents of the prescaler counter is cleared only when a value is written to TCC register.
This specification is subject to change without prior notice.
8
4. 1.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
